1. Technical Field of the Invention
The present invention relates to the design of digital systems in general, and particularly to apparatuses with multiple processors sharing a memory.
2. Description of Related Art
A number of digital systems comprise several processors to provide improved performances, particularly to overcome frequency limits of a single processor, and particularly for systems on chip. Each processor in such a system can synchronize its operation with the other processors and can share data through read/write operations in memory locations shared by all processors. In order to provide access to data with short response times or with a wide pass-band, each processor has a cache memory containing a local copy of data at a shared memory location. Since all processors can contain duplicate copies of the same memory location in their cache memory, it is necessary to maintain consistency between these cache memories. This consistency is assured by hardware and is used to optimize data exchanges by reducing the synchronization cost. Thus, when a processor modifies data in a cache memory, the cache memories of the other processors are automatically updated to reflect this change precisely.
FIG. 1 illustrates a snooping method on a global bus connecting processor cache memories with shared memory through a bridge chip. The digital system 1 in FIG. 1 has processors 2 and 3 provided with processing units 21 and 31 respectively, and cache memories 22 and 32 respectively. The system 1 also has a bus 4 that will facilitate operations to make cache memories 22 and 32 consistent. Bus 4 couples processors 2 and 3 to bridge 5, bridge 5 itself being coupled to a shared memory 6 and to an input/output channel 7. The interface of each processor with the bus has 120 bits, 64 bits being reserved for data and 56 bits being reserved for an address and the operation code.
Bridge 5 comprises a memory controller and a logic circuit to perform snooping transactions on the bus 4. The processors 2 and 3 and their cache memories 22 and 32 manage memory snooping transactions on the bus 4. Processors 2 and 3 use snooping data to keep the content of their cache memory consistent with the cache memory of the other processors.
Snooping is typically done using the MESI protocol. As a reminder, states according to the MESI protocol are associated with data in the cache memory of a processor. These states have the following meanings:
State M for modified means that the cache memory of the processor is the sole holder of a modified and valid copy of the data: neither the cache memories of other processors nor the main shared memory have this modified copy of the data.
State E for exclusive means that the cache memory of the processor and the main shared memory are holders of a copy of the valid data, but that the cache memories of the other processors do not hold this copy.
State S for shared means that the data in the cache memory of the processor may be held by the cache memory of other processors and that these data are also memorized in the main shared memory.
State I for invalid means that data in the cache memory of the processor are not valid.
Such a system has disadvantages. Several accesses to the cache memory are sometimes necessary to write some data previously in the state S. These accesses induce a complex microprocessor structure and a relatively high current consumption, which is penalizing for implementation in the form of systems on chip.
A need accordingly exists to solve one or several of these disadvantages.